1. Field of the Invention
The present invention relates to a fully differential flip-flop, and particularly to a fully differential flip-flop triggered on leading and trailing edges of a clock signal.
2. Description of Related Art
Known flip-flops used a method of a single-ended input and leading edge trigger to capture input data. However, the method of a single-ended input is often interfered by noises in a high frequency operation, and the method of a leading edge trigger will limit the operational speed of a flip-flop.
In a U.S. Pat. No. 4,629,909, entitled xe2x80x9cFLIP-FLOP FOR STORING DATA ON BOTH LEADING AND TRAILING EDGES OF CLOCK SIGNAL,xe2x80x9d disclosed a method to resolve the above problems. Even the prior art utilizes leading and trailing edges of a clock signal to capture a single input data, the application of the prior art is only suitable to a specific circuit, not all kinds of flip-flops.
In a U.S. Pat. No. 5,327,019, entitled xe2x80x9cDOUBLE EDGE SINGLE DATA FLIP-FLOP CIRCUITRY,xe2x80x9d disclosed a method to trigger on leading and trailing edges by utilizing two flip-flops and a logic circuit. The prior art costs much hardware, and its operational speed is limited due to passing a series of logic gates. Besides, the prior art utilizes a single-ended input that limits its ability to filter noises.
In a U.S. Pat. No. 5,250,858, entitled xe2x80x9cDOUBLE-EDGE TRIGGERED MEMORY DEVICE AND SYSTEM,xe2x80x9d disclosed a method to capture data on leading and trailing edges by utilizing two flip-flops and a switch circuit. Like the disadvantages as mentioned above, the prior art cost much hardware, and its operational speed is limited due to passing a series of logic gates.
A first object of the present invention is to propose a fully differential flip-flop capturing data on leading and trailing edges of a clock signal.
A second object of the present invention is to propose a fully differential flip-flop having the characteristic of differential inputs and well noise filter.
A third object of the present invention is to propose a low cost and high-speed fully differential flip-flop.
For achieving the above objects, the present invention proposes a fully differential double edge triggered flip-flop which stores and outputs first and second fully differential input values on leading and trailing edges of a clock. The fully differential double edge triggered flip-flop comprises a first fully differential master circuit, a second fully differential master circuit and a fully differential slave circuit. The first fully differential master circuit stores the first fully differential input value during the period from the leading edge to trailing edge of the clock. The second fully differential master circuit stores the second fully differential input value during the period from the trailing edge to leading edge of the clock. The fully differential slave circuit is electrically connected to outputs of the first and second fully differential master circuits. The fully differential slave circuit includes a second repeater as an output end of said fully differential double edge triggered flip-flop. The fully differential slave circuit outputs said first fully differential input value on the trailing edge of the clock, and outputs said second fully differential input value on the leading edge of the clock.